----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:58:39 12/02/2009 
-- Design Name: 
-- Module Name:    Decoder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Decoder is
    Port ( address : in  STD_LOGIC_VECTOR (1 downto 0);
           dec_out : out  STD_LOGIC_VECTOR (3 downto 0));
end Decoder;


architecture Behavioral of Decoder is
begin
	with address select
		dec_out <= "0001" when "00",
					  "0010" when "01",
					  "0100" when "10",
					  "1000" when "11",			
					  "0000" when others;

end Behavioral;

library IEEE;
use IEEE.std_logic_1164.all;

package mips_decoder is
	component Decoder
		Port ( address : in  STD_LOGIC_VECTOR (1 downto 0);
				 dec_out : out  STD_LOGIC_VECTOR (3 downto 0));
	end component;
end mips_decoder;
